1. Field of the Invention
The present invention relates to the field of integrated circuit analog storage devices.
2. Prior Art
Analog recording apparatus such as described in the U.S. Pat. No. 4,890,259 incorporates a dual plurality of sample and hold circuits. This architecture was developed to create the time intervals required to sequence through the analog recording operation, which in turn requires iterating through a series of perhaps hundreds of high voltage writing and comparing steps. As a result of the use of the pluralities of sample and hold circuits with, for example, 100 sample and hold nodes where each node is loaded at a different time, a practical problem results. The problem is that the voltage stored at each sample and hold node has a different amount of time to discharge before being stored into the nonvolatile array. As each node experiences leakage currents, each node will discharge a different amount before its voltage value is stored into the array. This distributed leakage action will result in an undesirable "sawtooth" voltage profile superimposed on the stored analog signal upon playback. For a voice playback, for example, there would be a loud buzz incorporated into the sound.
The amount of leakage is also strongly temperature dependant, as is known in the art. Such leakage currents double in magnitude roughly every 8 to 9 degrees Centigrade increase in temperature. In addition to the special requirements described above, the sensing system should also satisfy other requirements. For instance, the reference system should "reject" or put into the "common mode", temperature variations as those variations effect the storage cells. If voice information is recorded at a high temperature and played back at a lower temperature, the voice should not sound any different than the original recording. Similarly, to the extent that internal bias voltages which facilitate the array operation change with changes of the power supply voltages, such changes which also effect the behavior of the storage cells should not place any spurious information in the recorded information stream. This concept is known in the art as "power supply rejection." In short, the reference system must place into the common mode the thermal and power supply effects. Other factors which must be placed into the "common mode" and "rejected" are local variations in the storage cells due to wafer processing misalignment and cell layout orientation differences, as are known in the art.
Reference cells and columns of reference cells are known in the art to reject the affects of cell layout, process misalignment, temperature and power supply variations. In particular, floating gate memory cells are known to be used as references in the case of a digital nonvolatile memory application, as is described in U.S. Pat. No. 3,938,108. Columns of reference cells paralleling columns of memory cells are in effect what is described for a digital memory in the ISSCC paper entitled A 25ns 16K EPROM USING A 4-TRANSISTOR CELL (1985 ISSCC Digest of Technical Papers, pp. 162-163). Also in the neural network art, it is known that floating gate devices are "programmed" to provide an analog "weight" value, i.e., an equivalent to a variable resistor.